There have been widely used memory cartridges of a type in which an SRAM is backed up by means of battery. As great reduction in the consumption power of a DRAM is recently realized, however, there has also appeared in the market memory cartridges of another type wherein the DRAM is backed up by means of battery.
This is because the use of the SRAM can realize a memory capacity about four times larger than the use of the DRAM for the same size of memory. Accordingly, the use of the DRAM like the SRAM contributes greatly to increase in the memory capacity of the memory cartridge.
However, since the DRAM generally requires a refreshing time of several ten .mu. sec with a period of several msec, it is necessary to provide such a control circuit as to controllably adjust external access and refreshing operation. In addition, the memory cartridge of the SRAM type uses such a control signal as a chip enable signal having a format different from that used in the memory cartridge of the DRAM type and the SRAM type of memory cartridge is different in interface from the DRAM type of memory cartridge, which disadvantageously results in no compatibility between these SRAM and DRAM types.
A known example of a battery for backing up the operation of such a memory cartridge is taught in a magazine titled "NIKKEI ELECTRONICS" Aug. 10, 1987 (No. 427), pp. 167-183.
Conventional semiconductor memories capable of backing up information by means of a battery include a flip-flop type static memory comprising six or 4 MOS transistors and two high resistances and a dynamic memory comprising a single MOS transistor and a single information storage capacitance (of several ten fF). The static memory, in particular, is suitable as a battery backup device because it requires a stationary (DC) consumption current as small as several ten nA or .mu.A in a wait operation mode for the purpose of holding data. The dynamic memory, on the other hand, is suitably used in such a large-capacity memory system as called a semiconductor file which can have memory capacity four times larger than the static memory and can be more inexpensively made in cost per bit than the static memory when the same level of processing technique is employed. When the dynamic memory is back up by means of battery, however, this involves problems which follow. For this reason, the dynamic memory has not sufficiently been used as a portable semiconductor file memory.
Generally speaking, in the case of the dynamic memory, even when the memory shifts from its normal operation (active condition) mode wherein accessing is allowed for reading and writing operation to its wait operation (inactive condition) mode for the purpose of holding data, the memory must refresh (rewrite) data therein in a predetermined time. For example, in the case of a 1M bit memory, its refreshing period is set at usually eight msec due to the limitation of the data holding time of the memory cells so that all the memory cells can be refreshed through 512 refreshing operations.
First one of problems in the above data holding operation, i.e., in the wait operation, is that the average consumption current of the dynamic memory necessary for the wait operation is as large as several hundred .mu.A or mA. A second problem is that the peak level of a momentary AC current flowing in the refreshing-operation activation mode is as high as 100 mA or more.
As a measure against the former problem, it is most effective to prolong the refreshing period in the wait mode, as discussed in the aforementioned known literature.
The peak current as the latter problem is mainly due to the charging and discharging operation of the capacitances of bit lines connected to the memory cells. The total bit line capacitance for one refreshing operation amounts to several hundred pF and thus a momentarily large current flows through the memory. A memory system using the prior art dynamic memories causing such a peak current will be explained by referring to FIGS. 1A and 1B.
More specifically, FIG. 1A is an arrangement of a battery backup type memory system 102, and FIG. 1B shows waveforms of peak currents flowing through power supply lines for the respective memories and of a peak current flowing through a common power supply line corresponding to a sum of the respective memory peak currents.
In FIG. 1A, the memory system 102 is made in the form of an easily portable file, a reader/writer 104 performs reading and writing operation from and the memory system 102, a main power source 110 is a power supply means for the memory circuit 102, and a switch (SW) 114 is used to turn on or off the main power source 110. The memory system 102 includes a power supply circuit 108 for the memory system. The power supply circuit 108 in turn has an auxiliary power supply 112 for data backup as a second power supply means, diodes D.sub.1 and D.sub.2 for preventing a reverse current caused by a voltage drop in either one of the main and auxiliary power supplies 110 and 112 in the backup operation. The memory system 102 also includes memory chips M.sub.1 to M.sub.3, and capacitances C.sub.1 for removal of high frequency noise components in the power supply. In FIG. 1B, reference symbols i.sub.1 to i.sub.3 denote the waveforms of the peak currents for the respective memory chips with abscissa axis representing time t, and i.sub.t denotes a sum of the peak currents i.sub.1 to i.sub.3 (=i.sub.1 +i.sub.2 +i.sub.3) flowing through a common power supply line V.sub.cc. In the drawing, the illustrated peak currents i.sub.1 and i.sub.3 have respectively two peaks overlapped together. This results from the fact that the dynamic memory of the present embodiment performs its self refreshing operation and varies in its oscillation period. Reference symbols r.sub.1 and r.sub.2 are respectively internal resistances for the main and auxiliary power supplies 110 and 112. The auxiliary power supply 112 is usually a dry cell and its internal resistance r.sub.2 is as high as several .OMEGA.. The internal resistance r.sub.1 of the main power supply 110 is smaller by one figure than the internal resistance r.sub.2.
With such an arrangement, when the switch (SW) 114 is in its ON state, a current is supplied to the respective memory chips from the main power source 110 having the very low internal resistance r.sub.1 so that, even when the peak current is large, the memory system 102 can normally execute its refreshing operation. When the SW 114 is in its OFF state, i.e., when the main power source 110 is in its cut-off state, on the other hand, a current is supplied from the auxiliary power supply 112, but since the auxiliary power source 112 has the internal resistance r.sub.2 as high as several .OMEGA., the momentary discharging current ability is low. As a result, the power supply voltage V.sub.cc of the memory chips is remarkably reduced and the substrate potential is remarkably varied, which leads to the erroneous operation of the system.
As has been explained above, since the dynamic memory is large in its peak current, when such a small size battery as a button shaped battery having a large internal resistance is used, the momentary current supply ability becomes low. For this reason, even in the case of a small-capacity memory system, it becomes difficult to back up data for a long period of time or temporarily. Further, even when such a large-capacity cell as a lead battery is employed, it is difficult to realize the backup operation of such a large-capacity memory system that a multiplicity of dynamic memories are to be simultaneously refreshed, because the peak currents of the respective memory chips may be sufficiently considered to be overlapped together.
FIG. 2A and 2B respectively show an arrangement of a prior art dynamic memory system and a waveform of a peak current flowing through a power supply in its refreshing operation.
In detail, an LSI chip 210 of FIG. 2A includes a memory array 212, an X-direction address buffer 214, a Y-direction address buffer 216, a data input/output (I/O) buffer 218, an X-direction decoder (XD) 220, a Y-direction decoder (YD) 222, and a data input/output signal line 224. The LSI chip 210 further includes a refreshing controller 226 having therein a self-refreshing timer, an address counter and elements associated with the refreshing operation. The memory array 212 includes dynamic memory cells MC, n word lines W for selection of the memory cells arranged in an X direction, and m bit lines B of the memory cells arranged in a Y direction. In FIG. 2A, reference symbol AX.sub.i denotes a group of address signals for determining X-direction positions of the memory cells within the LSI chip 210, AY.sub.i a group of address signals for determining Y-direction positions of the memory cells, I/O.sub.i input/output data signals, REF a refreshing control signal. This REF signal is considered to be externally input directly from outside of the chip or to be internally generated. Further, symbol V.sub.cc is a power supply terminal in FIG. 2A, and a time T.sub.c on the waveform of a peak current flowing through the power supply terminal V.sub.cc in the refreshing operation represents a refreshing interval in FIG. 2B.
Generally speaking, in the case of a dynamic memory, it is necessary to refresh (rewrite) data within a predetermined time even when the memory system shifts from its normal operation (active condition) mode wherein accessing for reading and writing operations can be allowed to its wait operation (inactive condition) mode for holding the data. In the case of the aforementioned dynamic memory, when the refreshing control signal REF is activated, the memory system shifts from the normal mode to the wait mode, whereby a refreshing timer and an address counter incorporated in the chip are excited to automatically activate all the word lines sequentially and thereby refresh the data of all the memory cells. For example, in the case of a 1M bit memory, its refreshing period is set to be usually 8 msec due to the restriction of the data holding time of the memory cells so that all the memory cells can be refreshed through 512 refreshing operations. In this case, it is necessary to set one refreshing interval to be 8 msec per 512 and to select 2048 cells at one time at intervals of about 15 .mu.sec, and the memory is set to have 2048 (=m) bits in the X direction and 512 (=n) bits in the Y direction.
In the dynamic memory, for such data holding operation as mentioned above, all the memory cells have been refreshed within a predetermined time (for example, within 8 msec in the above example) due to the restriction of the data holding time of the memory cells, not only in the wait mode, but also in the activated memory mode or normal mode (write/read accessing mode).
This has resulted in that the substrate potential is remarkably varied and/or the power supply voltage is remarkably reduced due to the internal resistance of a power supply cell when the memory is back up by means of the battery, which leads to the erroneous operation of the system. To overcome such disadvantages, it has been considered to make small device constants to thereby reduce the power consumption of the internal circuit, or to operate the memory at a low speed to realize small charging/discharging currents and thereby reduction in the level of the peak current. The latter measure of reducing the peak current in the refreshing operation, however, has found difficulties in also attaining the high access time of the memory and thus it has been difficult to actually carry out the current reducing measure.